We've had a few requests for a Verilog Model of the Month, so here it is.
This month we'll present a model of an ADC. The example we present is for a bit ADC, but you can easily modify the digital output wordlength for any desired accuracy of ADC.
Note there are no conversion operators in this code as there was with the VHDL code - Verilog simply doesn't need them due to its absence of data typing. Note that we must specify a range for the returned value from the function in Verilog, in VHDL, a range constraint is not mandatory.
Real-valued ports are not allowed in Verilog so we must use a bit input port to maintain an accurate representation of the analogue signals. All of the required Verilog code is here, there are no references to other external code modules there are eight referenced packages in the VHDL code.
verilog code for Analog to digital converter
You are welcome to use the source code we provide but you must keep the copyright notice with the code see the Notices page for details. To download the Verilog source code for this month's Model of the Month, click here.
Friday 17 January Company Partners References Opportunities Contacts. Analog-to-Digital Converter OK. To download a simple test fixture, click here.
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